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-- Company: 
-- Engineer:
--
-- Create Date:   20:58:34 06/05/2010
-- Design Name:   
-- Module Name:   C:/Users/Tom/Documents/lcpd-scope/vhdl/project/ADConverter_Interface_TB.vhd
-- Project Name:  LCPD_Scope
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: ADConverter_Interface
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
 
ENTITY ADConverter_Interface_TB IS
END ADConverter_Interface_TB;
 
ARCHITECTURE behavior OF ADConverter_Interface_TB IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT ADConverter_Interface
    PORT(
         CLK_in : IN  std_logic;
         Data_A_in : IN  std_logic_vector(11 downto 0);
         Data_B_in : IN  std_logic_vector(11 downto 0);
         Data_A_out : OUT  std_logic_vector(11 downto 0);
         Data_B_out : OUT  std_logic_vector(11 downto 0);
         enable_in : IN  std_logic;
         newdata_out : OUT  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal CLK_in : std_logic := '0';
   signal Data_A_in : std_logic_vector(11 downto 0) := (others => '0');
   signal Data_B_in : std_logic_vector(11 downto 0) := (others => '0');
   signal enable_in : std_logic := '0';

 	--Outputs
   signal Data_A_out : std_logic_vector(11 downto 0);
   signal Data_B_out : std_logic_vector(11 downto 0);
   signal newdata_out : std_logic;

   -- Clock period definitions
   constant CLK_in_period : time := 100 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: ADConverter_Interface PORT MAP (
          CLK_in => CLK_in,
          Data_A_in => Data_A_in,
          Data_B_in => Data_B_in,
          Data_A_out => Data_A_out,
          Data_B_out => Data_B_out,
          enable_in => enable_in,
          newdata_out => newdata_out
        );

   -- Clock process definitions
   CLK_in_process :process
   begin
		CLK_in <= '0';
		wait for CLK_in_period/2;
		CLK_in <= '1';
		wait for CLK_in_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
	enable_in <= '1';
		Data_A_in <= "010101010101";
		Data_B_in <= "101010101010";
      wait for CLK_in_period*10;
		Data_B_in <= "010101010101";
		Data_A_in <= "101010101010";

      -- insert stimulus here 

      wait;
   end process;

END;
